Technology Options

n High, Medium and Low-end: The network servers can be classified into three categories—low-, mid-, and high-end. The low-end servers can be categorized into two types—the Standard Intel Architecture Servers (SIAS) and the RISC/Unix servers. Typically, these servers are priced below Rs 3-3.5 lakh while the Intel-based servers are priced up to Rs 40 lakh. The mid-range servers are primarily the non-Intel RISC/Unix servers and cost in the range of Rs 40 lakh to Rs 4 crore. The high-end servers are the mainframes, the most powerful of all servers and cost in excess of Rs 4 crore.

n Type of Processor Itanium: The 64-bit Itanium processor supports high transaction volumes, complex calculations and vast amounts of data and users. It has a 400 MHz bus, which is 12 bits wide and thus makes for greater data transfer rates. The 3 MB integrated Level 3 (L3) cache enables high processing rates and performance for faster online transaction processing, data analysis, and simulation and rendering. The processor also has advanced reliability features, including extensive error detection and correction on all of the processor’s major data structures.

Hammer: Hammer integrates a single or dual DDR memory controller with support for PC1600, PC2100, and the upcoming PC2700 DDR-SDRAM. This design reduces DRAM latency and increases memory bandwidth (up to 5.3 Gbps), capacity, and speed. Hammer includes AMD’s HyperTransport technology, which acts as a high-speed, low pin-count, asynchronous, point-to-point link connecting other Hammer chips. Scalability is key with support for 1P (processor), 2P (using ClawHammer chips), 4P, and 8P (using SledgeHammer chips). AMD’s Lego building approach enables glueless multiprocessing and gives a very cost-effective alternative to the ‘Big Iron’ approach.

n Instruction Set: A microprocessor has three basic characteristics—instruction, bandwidth and clock speed and can be categorized into a reduced instruction set computer (RISC) or a complex instruction set computer (CISC). A processor based on the RISC concept would use few instructions, which would require fewer transistors. By reducing the number of transistors and instructions to only those most frequently used, the computer would get more done in a shorter amount of time.

The argument is that the chip designers should make life easier for the programmer by reducing the amount of instructions required to program the CPU. Due to the high cost of memory and storage, CISC microprocessors were considered superior due to the requirements for small, fast code.