Technology is going beyond expectations and is making us greedier in terms of quantity and quality of service. We need everything on our mobile phone-from checking office mails to controlling the air conditioner. Initially we used to fantasize about these things, but now we are demanding them. Thanks to the wonder VLSI chip, which is driving the next level of innovation.

Till last year, the designing segment was more concerned about the size of end products. Though there were discussions about power and energy saving, they were not on the top of the to-do list. Now, smaller size has become the norm and the focus has shifted to green products. Undoubtedly, newer trends in the design industry are making the job tougher for engineers.

The 'Power' Design
Various requirements are making low power design the key trend for VLSI design. The key requirement is coming from mobility. One area where the convergence of applications is happening the most is the mobile terminal in users' hands. Today, the mobile is not just a telecommunications gadget. It is integrating the widely spread application lead by multimedia.

The second requirement comes from environmental needs. Again taking the example of handhelds, more energy efficiency can have incredible domino effect and hence less environmental footprint. This advocates the case for designs with multiple voltage islands.

While the voltage values don't necessarily vary for these islands, the implementation of different islands, each with its own power supply circuits, allows the switching on and switching off of circuitry in these islands, depending on when they need to be on or off. A good thing is that many VLSI Design CAD tools have begun to support such design methodologies, making it somewhat easier for the designer to implement their designs.

Given the current status of things, we have finally reached a point where “silicon area” is truly no longer the main focus from a design perspective. For the last twenty-five years, we have continuously focused on area reduction as the primary goal of VLSI designs.

Today, that goal is replaced by timing and power. Meeting the timing requirement is fundamental and essential for any design to work, while power has become the other essential constraint. Both these constraints are addressed today at the expense of area. For example, researchers are indicating that the 6-transistor memory cell, which has been used so extensively in designs, will no longer be useful at the lower than 0.9v requirements; instead, an 8-transistor cell would meet the requirement.

Move to Multi-core
The move to multi-CPU design architectures is a very fundamental and major trend that can be seen. There was a trend in high performance and high-end designs to push the frequency higher to achieve targets. And the company that implemented the highest frequency in its design, bragged about it and actually created this mindset among the consumer that the higher the frequency the better and more powerful the design.

But pushing frequency higher came with a cost-that of increasing power dissipation and energy consumption, thereby creating heat problems. Over the past couple of years, high-end CPUs for PCs and server systems moved to multi-core architecture. Interestingly, the trend is not limited to high-end servers or desktop CPU designs.

Even CPU cores being built for small form-factor devices like mobile phones, which traditionally were implemented with a focus on energy efficiency (to lengthen battery life), have now started to move to multi-core implementations. With greater computing demands on these CPU designs (voice, data, graphics, and video), the need to increase their performance without increasing their energy consumption is driving the trend toward multi-core designs.

While there is a lot of talk about 64-core, 128-core, all the way to hundreds of cores; from a practical perspective, the bulk of designs for general purpose processing would probably be using up to 4-8 cores, leaving the rest to be used for specific targeted problems/applications.

Energy Efficiency is Key
Energy efficiency is no longer just a buzzword. It is clearly a reality. All applications are moving toward things like multi-core architectures, which will improve energy efficiency. Fundamentally, “energy efficiency”, driven by the need to elongate battery life, is a key driving factor.

The initiatives taken to eliminate lead from manufactured products are definitely direct attempts to create environment-friendly products.

The environment-friendly focus would have a far greater impact at the end-product level, where the kind of materials used for making products like mobile phones need to be environment friendly. Of course, the chemicals used in semiconductor manufacturing are also quite detrimental to the environment and their proper disposal, as well as detoxification before releasing them back to the environment, is going to be a huge challenge.

Focus on Manufacturing
With 90 nm, it was indicated that designs have to be made keeping in mind the manufacturing process. For 65 nm and lower geometries, it is clearly a mandatory step. Designs are created after taking into consideration the manufacturing variability, be it in terms of geometry variations or other process parameters that affect design sensitivity.

Probably the most fundamental trend in the industry, driven more by business and less by technology, is the fact that more and more vertically-integrated device manufacturers (IDMs), which did their own designing and manufacturing, are becoming fab-lite or fab-less. They are moving away from internal manufacturing to foundry partnerships for smaller geometries like 65 nm, 45 nm, and 32 nm. Infineon, for example, did it with 65 nm technology, joining the IBM and Chartered alliance.

TI is doing it with 45 nm, going to TSMC for their manufacturing needs. Even Freescale and ST Micro have joined IBM, Chartered, Infineon, and the Samsung alliance. Thus, at the leading edge process geometries, Intel is probably the only IDM that designs and manufactures on its own.

TSMC and the foundries in the IBM alliance are two major camps supplying manufacturing services to the rest of the industry at the leading edge, while UMC, SMIC, and the others provide such services a little behind the leaders. This formation of the market forces has implications on the way the “design” is done.

At least, the basic common design IP (such as standard cells, embedded SRAMs, general purpose I/Os for SoCs) can now be built by third party suppliers like ARM Artisan, or Virage, while more complex, domain-specific design IP is built internal to design companies or sourced from third party IP design houses with expertise in those domain areas. This creates challenges of “integrating” all this IP from various sources to realize a design.

Redundancy is the other key design direction that improves the final device yield. For example, we can imagine a scenario where a full chip has to be discarded only because one of the millions of cells was faulty. In designs with redundancy, a few redundant cells or other elements are included in the chip so that in case one or more of the used cells are faulty, the cells can be replaced by the redundant cells already present in the chip, thereby, helping in improving the yield.

Regularity of design is another actively sought-after design direction that can help in reducing the size of the design. This will also help in improving the yield. Besides all this, there seems to be a great demand for re-configurable design. The steep increase in the cost of development of a chip, as we go for finer geometries along with the need for the shortening time-to-market, is putting a high demand on the re-configurability of designs so that the need for new derivative chips can be reduced. Here, various options are being developed; an FPGA embedded in the design is one such example.

Safety First
Rapid advances of the penetration of electronic systems in life-related areas like medical, electronics, and automotives require high reliability of these electronics systems, which, in turn, depends on the VLSI system integrated in them. Therefore, the need for the VLSI designs in terms of lower failure rates.

For Virtualization
Virtualization is another trend in the industry. It refers to the fact that multiple operating system (OS) environments are readily available on the system, enabling applications to be run seamlessly from the user's perspective on any of those OS environments as needed, giving the user a rich experience.

CPU designs would evolve to provide efficient support for virtualization, splitting efficiently the work between hardware and software.

Semiconductor manufacturers would like to keep customers “locked” to them, without giving them the option of second or third sourcing from another manufacturer. However, the design company would like to have multiple options to get their designs manufactured. It also allows them to negotiate favorable pricing. This tussle is having its own impact on the way VLSI design and manufacturing is done. The design company wants all manufacturers to create a similar process recipe so that the same design database (GDS) can be sent from one manufacturer to another to get the chip manufactured.

Lead manufactures like TSMC don't like to share their recipe since they want to keep the customer's business to themselves. From a process perspective, the “bulk CMOS” process is the main process being used for making most semiconductor chips today while there are other process technologies based on Gallium Arsenide and Indium Phosphide.

Most “low power” chips are based on the “bulk CMOS” process. For high performance applications, the SoI (Silicon on Insulator) process technology seems to be getting more and more accepted. This technology gives higher performance at similar energy efficiency compared with the “bulk CMOS” technology. It is expected that SoI would get adopted more and more on the high performance end to meet the application needs in the years to come.

Increased Complexity
The latest deep sub-micron technologies with shrinking dimensions and very high levels of integration are making the whole designing process very complex.

Temperature variations within the same die, voltage drops (IR), multiple power supplies, and very complex interconnects are some examples. Latest technologies are not only complex, but are highly sensitive. For example, a transistor parameter threshold voltage (Vt) in 45 nm is more sensitive as compared to previous technologies. This, coupled with the need for safer and more robust designs, is making the whole design very challenging.

As geometries shrink for newer silicon technologies, the leakage currents are substantially increasing. This is in direct conflict with the need for low power designs. Effectively managing leakage currents is a high design challenge.

The Future Looks Green
The multi-core trend will be a major trend influencing the industry. There is still a huge opportunity to create tools for designers so that they can build the whole system around these multi-core architectures on the hardware and software fronts. These tools and methodologies will allow efficient implementation of multi-threaded/multi-process software architectures to exploit multi-core hardware implementation.

The current VLSI process technologies are still fundamentally based on the MOS transistor and its operation. While it may not be at the end-of-life of the MOS transistor yet, it is possible to visualize that with 3-4 more generations leading us down to 10-12 nm would get in serious trouble. Not only that, each of these process technology generations will have huge challenges from a manufacturing perspective, requiring huge investments in re-tooling of manufacturing lines.

Semiconductor companies have moved to “liquid immersion” techniques for 45 nm-a major re-tooling effort. It will only get more challenging and expensive. We may end up staying with the MOS transistor and the available methods of manufacturing at whatever geometries (180 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 22 nm, 15 nm, 10 nm...) until the next disruptive breakthrough happens. The industry probably has about twenty years to come up with that next disruptive breakthrough.

Kumar Anshuman
anshumank@cybermedia.co.in